Modeling Transistor Mismatch

20 0740-7475/06/$20.00 © 2006 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers DIGITAL AND ANALOG ICS generally rely on the concept of matched behavior between identically designed devices.1-3 Time-independent variations between identically designed transistors, called mismatch, affect the performance of most analog and even digital MOS circuits. In analog circuits, the spread in the DC characteristics of supposedly matched transistors produces inaccurate or even anomalous circuit behavior.2 In digital circuits, transistor mismatch leads to propagation delays whose spread can amount to several gate delays for deep-submicron technologies.2,3 As Meindl predicted, “Variations will set the ultimate limits on scaling of MOSFETs.”4 Shrinking MOSFET dimensions and a reduced supply voltage make matching limitations even more important. Mismatch results from either systematic or stochastic (random) effects. Systematic effects originate from either poor layout or uncontrollable variation during an IC’s fabrication. Systematic mismatch can originate from equipment-induced nonuniformities such as temperature gradients and photomask size differences across the wafer. Systematic effects are important for large distances, but appropriate layout techniques can minimize them. Random mismatch refers to local variation in parameters such as doping concentration, mobility, oxide thickness, and polysilicon granularity. Random mismatch dominates systematic mismatch for short distances (that is, distances of the same order as the transistor size as opposed to the die size) and is generally assumed to display a Gaussian distribution characterized by the random mismatch’s standard deviation. Stochastic mismatch requires a model to guide the IC designer’s sizing and biasing strategies. This article focuses on the analysis of mismatch in MOS transistors resulting from random fluctuations of the dopant concentration, first studied by Keyes.5 Today, we recognize these fluctuations as the main cause of mismatch in bulk CMOS transistors.